Chapter 148: Physical AI

Dojin Industries Underground.

An empty laboratory.

Only the chair I’m sitting on creaks faintly.

The surroundings are silent.

A few sheets of white paper and a pen lie haphazardly on the table.

It’s been a relentless race against time.

From glass lens regeneration to mobile lenses, actuators, and camera modules.

Batteries, displays, and even entering the smartphone market.

I’ve been running nonstop to topple a giant fortress.

And I’ve achieved some results.

But to completely dismantle the fortress, there’s one mountain I must climb.

“Semiconductors.”

Right now, I have no infrastructure for semiconductors.

I’ve made astronomical amounts of money through business and investments.

But it’s all been poured into expanding market share and advancing existing technologies.

There’s simply no room to invest in semiconductors.

However, funding through an IPO or external investment isn’t an option.

‘The fortress’s semiconductor technology isn’t something that can be caught up with just money.’

In terms of technical ability, I’m not behind.

But turning that technology into a real product and building the infrastructure for mass production isn’t something money alone can solve.

The time it takes to establish the infrastructure, stabilize the production line, and secure yields.

By then, the fortress will likely have already moved on to the next stage.

Rushing into the semiconductor market unprepared could expose my weaknesses to the fortress.

So, my plan is to build some infrastructure here before transitioning to mass production.

What if I develop the production infrastructure first, the equipment to realize the semiconductor technology I envision a decade from now, and then declare my market entry?

I’m confident that even a fortress with overwhelming technology wouldn’t stand a chance.

That’s why I’m thinking of developing not just any semiconductor, but AI semiconductors.

I slowly write on the paper on the table.

[AI Semiconductor Development]

[Computational Optimization, Low-Power Design, Edge Computing, Autonomous Learning Structure]

Not right now, but in a few years, securing AI semiconductor technology will be essential to survive in the semiconductor market.

Not just smartphones, but humanoid robots, autonomous driving, factory automation, data center servers—

AI semiconductors are indispensable in every field.

To do that, I need to…

‘Build the facilities first.’

Unlike standard semiconductors like memory chips or APs (Application Processors),

AI semiconductors require a neural network computational structure that can process learning, inference, and data in real-time.

And to achieve this, highly advanced microfabrication is essential.

“5nm process. No, let’s start directly with 2nm.”

The last thing I led as the head of strategic planning at the fortress was 2nm process technology.

‘First, building the design and process lines myself is too much… I need to start with a testbed.’

I immediately pick up the phone.

I search through my contacts and find a name.

Team Leader Park Sang-bae, recruited from Yoonseong Plus, who led the development of numerous equipment with me, including the active aligner.

-“President, what’s the matter?”

Team Leader Park’s voice comes through.

“Where are you now?”

-“I’m on the third floor of the research building. I was finalizing the review of the automated lens resolution inspection equipment you mentioned last time.”

Team Leader Park’s response reminds me of what I instructed.

Currently, lens resolution inspection is done by quantifying PIMA charts, and each device can inspect fewer than 2,000 lenses per day.

To improve this, I instructed the development of a dedicated device called MTTF.

It seems to be nearing completion.

“I have something important to discuss, so could you come to Dojin Industries right now?”

-“Yes, I understand.”

After hanging up, silence envelops the lab again.

The words written on the paper catch my eye.

[AI Semiconductor Development]

[Computational Optimization, Low-Power Design, Edge Computing, Autonomous Learning Structure]

‘Even if I handle the design, the real issue is the process and equipment.’

Creating the equipment to implement a 2nm process is no simple task.

Soon, Team Leader Park arrives, and I take him to the underground lab via the top-floor elevator of Dojin Industries.

Except for Park Cheol-jin, who built this place, he’s the first visitor.

“Is… is this place… here?”

“It’s a secret space I built for my hobby. Please keep it confidential.”

Of course, to develop semiconductors, I plan to reveal this place to a few others, including Chilbong.

“But why are you showing me this place all of a sudden?”

Leaving Team Leader Park’s question behind, I walk over to the whiteboard in front.

I pick up a marker and draw a simple diagram.

The basic layout of the chip, neural network computational structure, and memory and computational unit placement.

“Is this… an AP blueprint?”

“Yes, but it’s not just any AP—it’s an AI semiconductor.”

“AI semiconductor? What’s that?”

Team Leader Park looks puzzled by the unfamiliar term.

It’s understandable, as the term “AI semiconductor” only became familiar after the launch of ChatGPA, a conversational AI service.

“Think of it as a computational device optimized for deep learning. A semiconductor optimized for data learning and inference.”

Team Leader Park, understanding my words, examines the diagram I drew and his eyes widen.

“Co… could this be a product requiring 2nm process technology?”

“Yes, that’s why I called you. To make the semiconductor I want, we need to develop the equipment first.”

Team Leader Park’s pupils shake as if hit by an earthquake.

“As far as I know, the technology currently in mass production at the fortress is at the 20nm level. Are you really talking about 2nm?”

As far as I know, the A-Core series produced by the fortress uses 20nm process technology.

“The fortress’s research institute is actively developing 10nm technology, and they’ve just started researching 3nm process technology.”

Of course, it’ll take another decade for 3nm technology to be applied to mass production.

“And yet, you’re planning to develop 2nm production equipment now?”

Team Leader Park shakes his head, thinking it’s impossible.

“I’ll help you!”

His expression changes at the offer of help.

We’ve successfully developed numerous pieces of equipment together that were once thought impossible, like the active aligner, liquid metal damper, and MTTF device.

“What should I do first?”

Team Leader Park’s gaze shifts to the chip structure diagram on the whiteboard.

The structure is vastly different from a conventional AP.

The transistor density is so high that it’s impossible to achieve with current equipment,

and the data transmission paths between the computational and memory units are equally complex.

“First, we need to redesign the entire process, starting with the basic exposure equipment.”

I write the first item on the whiteboard.

[Exposure Equipment (Extreme Ultraviolet Lithography, EUV) Design and Development]

“This seems like a completely different structure from existing exposure equipment.”

“Yes. To create a semiconductor optimized for AI computation, we need more precise EUV equipment to increase circuit density.”

“More precise equipment…”

“Standard exposure equipment can’t handle a 2nm process, so we need to design entirely new equipment.”

Team Leader Park’s expression turns serious.

“The cost alone is staggering, and this isn’t something we can develop overnight.”

I agree.

“That’s why I’m estimating about five years to establish the entire production infrastructure.”

It might seem long,

but if we can establish a 2nm production system within five years, I’ll have a formidable competitive edge in the semiconductor market.

“What other equipment do we need to develop?”

I continue listing the necessary equipment.

[Deposition and Etching Equipment]

Equipment for depositing and etching transistors at the nanometer level.

Especially for the precise deposition of neural network computational and memory units, development is essential.

“We also need to develop CMP equipment.”

Unlike conventional APs, integration between computational and memory units is crucial for AI semiconductors.

To eliminate microscopic defects when connecting these units, ultra-precise CMP equipment (chemical mechanical polishing) is essential.

Team Leader Park sighs just hearing about it.

“…I can’t even fathom how much developing this equipment will cost.”

“It’ll cost trillions, but I’ll figure out the funding. You focus on forming a task force for equipment development.”

“President, do you have any reference materials for equipment development?”

I smile and open a drawer in the lab.

Based on future semiconductor technology I’ve recorded in my regression,

I’ve designed the technology myself. It’s not perfect, but it contains all the core technology, so it’s not impossible to build.

“We need to prioritize what’s in the notebook first.”

“Should we aim to establish a small-scale process line capable of producing prototypes?”

Team Leader Park’s words align perfectly with my thoughts.

“Let’s aim to produce a prototype within three years.”

“Understood. I’ll try to expedite the schedule as much as possible.”

I shake my head.

“It’s more important to build proper equipment than to rush the schedule.”

“…Understood.”

After Team Leader Park leaves,

I write on the paper again.

[AI Semiconductor Development – Phase 1: Research Process Line Establishment]

[Goal: Design and Build a Small-Scale 2nm Process Line]

[Estimated Time: 36 Months]

[AI Semiconductor Development – Phase 2: Design and Computational Structure Optimization]

[Goal: Develop Test Chips]

[Core Content]

-Autonomous learning optimization structure design based on data from key services like Lunar and KTalk

-Custom microarchitecture for Edge AI, Server AI, and Humanoid AI

-On-device learning…

[Estimated Time: 18–24 Months]

[AI Semiconductor Development – Phase 3: Conversational AI Platform Implementation]

[Goal: Develop and Implement a Conversational AI Engine Based on AI Semiconductors]

[Core Content]

-Implement high-performance conversational AI based on AI semiconductors developed in Phase 2.

-Build a hyper-personalized language model integrated with Lunar and KTalk.

-Develop a universal LLM (Local Large Language Model) operable across smartphones, tablets, PCs, and servers.

[Estimated Time: 18 Months]

[AI Semiconductor Development – Phase 4: Physical AI Implementation]

[Goal: Robotics Technology Fusion → Humanoid…]

…